nongye/STM32F103_App1/Src/stm32f1xx_it.c

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/* USER CODE BEGIN Header */
/**
******************************************************************************
* @file stm32f1xx_it.c
* @brief Interrupt Service Routines.
******************************************************************************
* @attention
*
* <h2><center>&copy; Copyright (c) 2019 STMicroelectronics.
* All rights reserved.</center></h2>
*
* This software component is licensed by ST under BSD 3-Clause license,
* the "License"; You may not use this file except in compliance with the
* License. You may obtain a copy of the License at:
* opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
/* USER CODE END Header */
/* Includes ------------------------------------------------------------------*/
#include "main.h"
#include "stm32f1xx_it.h"
/* Private includes ----------------------------------------------------------*/
/* USER CODE BEGIN Includes */
#include "string.h"
/* USER CODE END Includes */
/* Private typedef -----------------------------------------------------------*/
/* USER CODE BEGIN TD */
/* USER CODE END TD */
/* Private define ------------------------------------------------------------*/
/* USER CODE BEGIN PD */
/* USER CODE END PD */
/* Private macro -------------------------------------------------------------*/
/* USER CODE BEGIN PM */
/* USER CODE END PM */
/* Private variables ---------------------------------------------------------*/
/* USER CODE BEGIN PV */
/* USER CODE END PV */
/* Private function prototypes -----------------------------------------------*/
/* USER CODE BEGIN PFP */
/* USER CODE END PFP */
/* Private user code ---------------------------------------------------------*/
/* USER CODE BEGIN 0 */
/* USER CODE END 0 */
/* External variables --------------------------------------------------------*/
extern DMA_HandleTypeDef hdma_usart3_rx;
extern DMA_HandleTypeDef hdma_uart4_rx;
extern UART_HandleTypeDef huart3;
extern UART_HandleTypeDef huart4;
extern UART_HandleTypeDef huart2;
extern UART_HandleTypeDef huart1;
extern DMA_HandleTypeDef hdma_usart2_rx;
extern uint8_t uart2_dma_buf[64];
extern uint8_t uart2_frame_buf[64];
extern volatile uint16_t uart2_frame_len;
extern volatile uint8_t uart2_frame_ready;
/* USER CODE BEGIN EV */
#include "network.h"
/* USER CODE END EV */
/******************************************************************************/
/* Cortex-M3 Processor Interruption and Exception Handlers */
/******************************************************************************/
/**
* @brief This function handles Non maskable interrupt.
*/
void NMI_Handler(void)
{
/* USER CODE BEGIN NonMaskableInt_IRQn 0 */
/* USER CODE END NonMaskableInt_IRQn 0 */
/* USER CODE BEGIN NonMaskableInt_IRQn 1 */
/* USER CODE END NonMaskableInt_IRQn 1 */
}
/**
* @brief This function handles Hard fault interrupt.
*/
void HardFault_Handler(void)
{
/* Ӳ<><D3B2><EFBFBD><EFBFBD><EFBFBD>󶵵ף<F3B6B5B5><D7A3><EFBFBD><EFBFBD><EFBFBD>ѯ<EFBFBD><D1AF>ʽ<EFBFBD><CABD> USART1 <20><>һ<EFBFBD><D2BB><EFBFBD><EFBFBD>Ϣ<EFBFBD><CFA2><EFBFBD>ж<EFBFBD><D0B6>Ѳ<EFBFBD><D1B2>ɿ<EFBFBD><C9BF><EFBFBD><EFBFBD><EFBFBD>
* ֮<EFBFBD><EFBFBD>ͣ<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> IWDG <EFBFBD><EFBFBD>λ<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ڿ<EFBFBD><EFBFBD><EFBFBD> "HARD FAULT" <EFBFBD><EFBFBD>˵<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>Ӳ<EFBFBD><EFBFBD><EFBFBD><EFBFBD> */
{
static const char msg[] = "\r\n!!! HARD FAULT, wait IWDG reset !!!\r\n";
for (unsigned i = 0; i < sizeof(msg) - 1; i++) {
while ((USART1->SR & USART_SR_TXE) == 0) { }
USART1->DR = msg[i];
}
}
while (1)
{
/* USER CODE BEGIN W1_HardFault_IRQn 0 */
/* USER CODE END W1_HardFault_IRQn 0 */
}
}
/**
* @brief This function handles Memory management fault.
*/
void MemManage_Handler(void)
{
/* USER CODE BEGIN MemoryManagement_IRQn 0 */
/* USER CODE END MemoryManagement_IRQn 0 */
while (1)
{
/* USER CODE BEGIN W1_MemoryManagement_IRQn 0 */
/* USER CODE END W1_MemoryManagement_IRQn 0 */
}
}
/**
* @brief This function handles Prefetch fault, memory access fault.
*/
void BusFault_Handler(void)
{
/* USER CODE BEGIN BusFault_IRQn 0 */
/* USER CODE END BusFault_IRQn 0 */
while (1)
{
/* USER CODE BEGIN W1_BusFault_IRQn 0 */
/* USER CODE END W1_BusFault_IRQn 0 */
}
}
/**
* @brief This function handles Undefined instruction or illegal state.
*/
void UsageFault_Handler(void)
{
/* USER CODE BEGIN UsageFault_IRQn 0 */
/* USER CODE END UsageFault_IRQn 0 */
while (1)
{
/* USER CODE BEGIN W1_UsageFault_IRQn 0 */
/* USER CODE END W1_UsageFault_IRQn 0 */
}
}
/**
* @brief This function handles Debug monitor.
*/
void DebugMon_Handler(void)
{
}
/* SVC_Handler / PendSV_Handler / SysTick_Handler <20><><EFBFBD><EFBFBD> FreeRTOS port.c <20>
* <EFBFBD><EFBFBD>FreeRTOSConfig.h <EFBFBD><EFBFBD> vPortSVCHandler/xPortPendSVHandler/xPortSysTickHandler
* <EFBFBD><EFBFBD>ӳ<EFBFBD> CMSIS <EFBFBD><EFBFBD>׼<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>˴<EFBFBD><EFBFBD><EFBFBD><EFBFBD>ٶ<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ظ<EFBFBD><EFBFBD><EFBFBD>
* HAL ʱ<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> TIM2<EFBFBD><EFBFBD>SysTick <EFBFBD><EFBFBD> FreeRTOS <EFBFBD><EFBFBD> RTOS tick<EFBFBD><EFBFBD><EFBFBD><EFBFBD> */
/**
* @brief This function handles TIM2 global interrupt (HAL timebase).
*/
extern TIM_HandleTypeDef htim2;
void TIM2_IRQHandler(void)
{
/* USER CODE BEGIN TIM2_IRQn 0 */
/* USER CODE END TIM2_IRQn 0 */
HAL_TIM_IRQHandler(&htim2);
/* USER CODE BEGIN TIM2_IRQn 1 */
/* USER CODE END TIM2_IRQn 1 */
}
/******************************************************************************/
/* STM32F1xx Peripheral Interrupt Handlers */
/* Add here the Interrupt Handlers for the used peripherals. */
/* For the available peripheral interrupt handler names, */
/* please refer to the startup file (startup_stm32f1xx.s). */
/******************************************************************************/
/**
* @brief This function handles USART1 global interrupt.
*/
void USART1_IRQHandler(void)
{
/* USER CODE BEGIN USART1_IRQn 0 */
/* USER CODE END USART1_IRQn 0 */
HAL_UART_IRQHandler(&huart1);
/* USER CODE BEGIN USART1_IRQn 1 */
/* USER CODE END USART1_IRQn 1 */
}
/**
* @brief This function handles DMA1 channel3 global interrupt.
*/
void DMA1_Channel6_IRQHandler(void)
{
HAL_DMA_IRQHandler(&hdma_usart2_rx);
}
void DMA1_Channel3_IRQHandler(void)
{
/* USER CODE BEGIN DMA1_Channel3_IRQn 0 */
/* USER CODE END DMA1_Channel3_IRQn 0 */
HAL_DMA_IRQHandler(&hdma_usart3_rx);
/* USER CODE BEGIN DMA1_Channel3_IRQn 1 */
/* USER CODE END DMA1_Channel3_IRQn 1 */
}
/**
* @brief This function handles DMA2 channel3 global interrupt (UART4_RX / WiFi).
*/
void DMA2_Channel3_IRQHandler(void)
{
/* USER CODE BEGIN DMA2_Channel3_IRQn 0 */
/* USER CODE END DMA2_Channel3_IRQn 0 */
HAL_DMA_IRQHandler(&hdma_uart4_rx);
/* USER CODE BEGIN DMA2_Channel3_IRQn 1 */
/* USER CODE END DMA2_Channel3_IRQn 1 */
}
/**
* @brief This function handles UART4 global interrupt (WiFi ESP-01S, DMA+IDLE).
*/
void UART4_IRQHandler(void)
{
/* USER CODE BEGIN UART4_IRQn 0 */
uint32_t temp;
if ((__HAL_UART_GET_FLAG(&huart4, UART_FLAG_IDLE) != RESET))
{
/* <20><><EFBFBD><EFBFBD>״̬<D7B4>Ĵ<EFBFBD><C4B4><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ݼĴ<DDBC><C4B4><EFBFBD> */
__HAL_UART_CLEAR_IDLEFLAG(&huart4);
/* ʧЧDMA<4D><41><EFBFBD><EFBFBD> */
HAL_UART_DMAStop(&huart4);
/* <20><>ȡ<EFBFBD><C8A1><EFBFBD>ճ<EFBFBD><D5B3>ȣ<EFBFBD><C8A3>ܴ<EFBFBD>С<><CAA3><EFBFBD><EFBFBD>С */
temp = huart4.hdmarx->Instance->CNDTR;
Rx_Len = Rx_Max - temp;
/* ׷<>ӵ<EFBFBD> U2_CopyBuff <20><> AT ָ<><D6B8>/MQTT <20><><EFBFBD>Ľ<EFBFBD><C4BD><EFBFBD><EFBFBD><EFBFBD>
* <EFBFBD><EFBFBD> USART3 <EFBFBD><EFBFBD><EFBFBD><EFBFBD>ͬһ<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> WiFi <EFBFBD><EFBFBD><EFBFBD>˼<EFBFBD><EFBFBD><EFBFBD>ʱ<EFBFBD><EFBFBD>׷<EFBFBD>ӣ<EFBFBD><EFBFBD><EFBFBD>ֹ<EFBFBD><EFBFBD>·<EFBFBD><EFBFBD><EFBFBD>ݽ<EFBFBD>֯ */
if (Rx_Len > 0 && NET_GetActiveBackend() == NET_BACKEND_WIFI &&
(U2_CopyIndex + Rx_Len) < (U2_COPY_SIZE - 1))
{
memcpy(U2_CopyBuff + U2_CopyIndex, Rx_Buf, Rx_Len);
U2_CopyIndex += Rx_Len;
U2_CopyBuff[U2_CopyIndex] = '\0';
U2_CopyFlag = 1;
}
/* ʹ<>ܽ<EFBFBD><DCBD><EFBFBD>DMA<4D><41><EFBFBD><EFBFBD> */
HAL_UART_Receive_DMA(&huart4, Rx_Buf, Rx_Max);
}
/* USER CODE END UART4_IRQn 0 */
HAL_UART_IRQHandler(&huart4);
/* USER CODE BEGIN UART4_IRQn 1 */
/* USER CODE END UART4_IRQn 1 */
}
/**
* @brief This function handles USART2 global interrupt.
*/
void USART2_IRQHandler(void)
{
/* USER CODE BEGIN USART2_IRQn 0 */
/* 485 <20><>֡<EFBFBD><D6A1><EFBFBD><EFBFBD><E7A3BA>·<EFBFBD><C2B7>Ĭ<EFBFBD><C4AC><EFBFBD><EFBFBD> IDLE<4C><45>DMA <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>һ֡<D2BB><D6A1><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> */
if (__HAL_UART_GET_FLAG(&huart2, UART_FLAG_IDLE) != RESET)
{
__HAL_UART_CLEAR_IDLEFLAG(&huart2);
HAL_UART_DMAStop(&huart2);
uint16_t len = (uint16_t)(sizeof(uart2_dma_buf) - huart2.hdmarx->Instance->CNDTR);
if (len > 0 && !uart2_frame_ready) {
memcpy(uart2_frame_buf, uart2_dma_buf, len);
uart2_frame_len = len;
uart2_frame_ready = 1;
}
HAL_UART_Receive_DMA(&huart2, uart2_dma_buf, sizeof(uart2_dma_buf));
__HAL_UART_ENABLE_IT(&huart2, UART_IT_IDLE);
}
/* USER CODE END USART2_IRQn 0 */
HAL_UART_IRQHandler(&huart2);
/* USER CODE BEGIN USART2_IRQn 1 */
/* USER CODE END USART2_IRQn 1 */
}
/**
* @brief This function handles USART3 global interrupt.
*/
void USART3_IRQHandler(void)
{
/* USER CODE BEGIN USART3_IRQn 0 */
uint32_t temp;
if ((__HAL_UART_GET_FLAG(&huart3, UART_FLAG_IDLE) != RESET))
{
/* <20><><EFBFBD><EFBFBD>״̬<D7B4>Ĵ<EFBFBD><C4B4><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ݼĴ<DDBC><C4B4><EFBFBD> */
__HAL_UART_CLEAR_IDLEFLAG(&huart3);
/* ʧЧDMA<4D><41><EFBFBD><EFBFBD> */
HAL_UART_DMAStop(&huart3);
/* <20><>ȡ<EFBFBD><C8A1><EFBFBD>ճ<EFBFBD><D5B3>ȣ<EFBFBD><C8A3>ܴ<EFBFBD>С<><CAA3><EFBFBD><EFBFBD>С */
temp = huart3.hdmarx->Instance->CNDTR;
Rx_Len = Rx_Max - temp;
/* ׷<>ӵ<EFBFBD> U2_CopyBuff <20><> AT ָ<><D6B8>/MQTT <20><>Ϣ<EFBFBD><CFA2><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
* <EFBFBD><EFBFBD> UART4 <EFBFBD><EFBFBD><EFBFBD><EFBFBD>ͬһ<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> 4G <EFBFBD><EFBFBD><EFBFBD>˼<EFBFBD><EFBFBD><EFBFBD>ʱ<EFBFBD><EFBFBD>׷<EFBFBD>ӣ<EFBFBD><EFBFBD><EFBFBD>ֹ<EFBFBD><EFBFBD>·<EFBFBD><EFBFBD><EFBFBD>ݽ<EFBFBD>֯ */
if (Rx_Len > 0 && NET_GetActiveBackend() == NET_BACKEND_4G &&
(U2_CopyIndex + Rx_Len) < (U2_COPY_SIZE - 1))
{
memcpy(U2_CopyBuff + U2_CopyIndex, Rx_Buf, Rx_Len);
U2_CopyIndex += Rx_Len;
U2_CopyBuff[U2_CopyIndex] = '\0';
U2_CopyFlag = 1;
}
/* ʹ<>ܽ<EFBFBD><DCBD><EFBFBD>DMA<4D><41><EFBFBD><EFBFBD> */
HAL_UART_Receive_DMA(&huart3, Rx_Buf, Rx_Max);
}
/* USER CODE END USART3_IRQn 0 */
HAL_UART_IRQHandler(&huart3);
/* USER CODE BEGIN USART3_IRQn 1 */
/* USER CODE END USART3_IRQn 1 */
}
/* USER CODE BEGIN 1 */
/* USER CODE END 1 */
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/